In a typical substrate conduction arrangement, current passes from field effect devices formed on an integrated circuit die to the VSS power supply via the substrate of the integrated circuit die. This advantageously reduces the number of VSS bond pads needed on the front side of the die, and in some cases entirely eliminates the need for such bond pads. Substrate conduction also provides other advantages, including a reduction in power supply lead inductance, as well as alleviation of ringing and ground bounce problems. Single-die substrate conduction arrangements are described in greater detail in U.S. Pat. No. 4,947,228, issued Aug. 7, 1990 in the name of inventor T. J. Gabara and entitled “Integrated Circuit Power Supply Contact,” the disclosure of which is incorporated by reference herein.
FIG. 1 illustrates an example of conventional single-die substrate conduction of the type described in the above-cited U.S. patent. It should be understood that this drawing, and other drawings herein, are considerably simplified for clarity of description. As shown, an integrated circuit 100 comprises a P+ substrate 102 on which a p-type epitaxial layer 104 is formed. The epitaxial layer is lightly doped relative to the substrate, and thus provides a high resistivity layer. A tub region 106, of p-type conductivity in this example, is formed in the epitaxial layer 104, and a highly-doped P+ tub tie 108 is formed in the tub region 106. The tub tie 108 is connected to a VSS bus 110 of the integrated circuit, which is coupled to terminals of field effect devices not explicitly shown in this simplified drawing. The integrated circuit 100 further includes a VDD bond pad 112 and a signal bond pad 114, which are coupled to a VDD bonding wire 116 and a signal bonding wire 118, respectively. The VDD bonding wire 116, VDD bond pad 112, signal bonding wire 118, signal bond pad 114, and the substrate conduction path formed by the VSS bus 110, P+ tub tie 108 and p-tub 106, can be replicated numerous times on a die.
Although not shown in FIG. 1, a metallic layer may be formed on the back of the substrate 102, that is, on a side of the substrate opposite the epitaxial layer. Such a metallic layer is coupled to a VSS power supply external to the integrated circuit, which is also not shown.
In the FIG. 1 arrangement, a current I passes through the integrated circuit from a VDD supply external to the integrated circuit via VDD bonding wire 116 through VDD bond pad 112 to terminals of field effect devices. Assuming for simplicity of illustration that no current enters or leaves the integrated circuit via signal leads, such as signal bonding wire 118, the current I passes from other terminals of the field effect devices to the VSS bus 110. From the VSS bus, the current I passes through the tub tie 108, p-tub 106 and epitaxial layer 104, and finally through the substrate 102 to an external VSS supply which is not shown in the drawing. The direction of substrate conduction is indicated by the arrow 120. Thus, in this substrate conduction arrangement, the VSS current from the field effect devices flows through the substrate 102, rather than through VSS bonding wires.
A problem with conventional substrate conduction is that the technique was developed in the context of single-die integrated circuits. However, numerous integrated circuits have recently been developed which utilize a stacked-die configuration, in which multiple integrated circuit die are stacked on top of one another with at least a partial overlap between adjacent die. Although the above-noted advantages of single-die substrate conduction would also be desirable in the stacked-die context, it has not heretofore been apparent whether or how substrate conduction could be provided in such a context.
Accordingly, a need exists for techniques for providing substrate conduction in an integrated circuit having a stacked-die configuration.